In a system performing recording/playback of digital data, errors may occur in the data during playback or recording, and therefore, it is necessary to perform error correction, and error detection for checking as to whether the performed error correction is correct or not.
For example, during recording/playback of a DVD as an optical recording medium, a method called ECC (Error Correcting Code) and a method called EDC (Error Detecting Code) are used for error correction and error detection, respectively.
The ECC processing is executed in units of error correcting code blocks (hereinafter, referred to as “ECC blocks”), and each ECC block comprises 16 sectors as shown in FIG. 11. The EDC processing is executed in units of sectors in the ECC blocks, and one sector has a structure as shown in FIG. 12.
Hereinafter, the outline of ECC decoding will be described with reference to FIGS. 11 to 14, taking, as an example, a case where data recorded in a DVD as an optical recording medium are subjected to error correction.
Initially, when subjecting the data recorded on the DVD to error correction, ECC-coded data which are read from the DVD are decoded, and the read data are subjected to error correction in a C1 direction or a C2 direction shown in FIG. 11. At this time, a position polynomial and a numeric polynomial are generated from the ECC-decoded data, and the roots thereof are obtained to derive error data positions and error data numerical values.
When code strings in one ECC block are subjected to error correction in the C1 direction or the C2 direction, if errors that exceed the error correction ability exist in the data, the data code strings that exceed the error correction ability are regarded as uncorrectable code strings as shown in FIG. 13, and information relating to the uncorrectable code strings is stored as information of lost positions.
After error correction has ended for all the code strings in the one ECC block in the C1 direction or the C2 direction shown in FIG. 11, error correction is again carried out for the code strings in the one ECC block in the direction different from that for the previous error correction (C2 direction or C1 direction) using the lost position information.
When performing error correction using the lost position information, since the error data positions have previously been known, it is only necessary to obtain a numerical polynomial when generating the above-mentioned polynomial. As the result, the error correction ability can be enhanced.
For example, it is assumed that, when error correction is initially carried out in the C1 direction for all the code strings in the one ECC block as shown in FIG. 13, the 50th, 90th, 130th, and 200th rows in the one ECC block are uncorrectable code strings. Thereafter, as shown in FIG. 14, error correction is carried out in the C2 direction that is different from the direction for the first error correction. At this time, on the basis of the lost position information indicating the uncorrectable code strings, the 50th, 90th, 130th, and 200th bytes in the one ECC block are designated as lost position information, whereby the error correction ability in the C2 direction can be enhanced. This method realizes error correction without degrading the correction ability for burst errors that occur in the transmission system.
When performing error correction and error detection for data code strings, conventionally, EDC operation is carried out in sector units in one ECC block after the ECC processing for one ECC block has ended.
Hereinafter, the outline of the ECD operation will be described with reference to FIGS. 14 and 15. FIG. 15 is a diagram illustrating the construction of an EDC operation circuit, wherein a 4-byte-input EDC operation circuit is shown.
Initially, an EDC operational formula is as follows.
            EDC      ⁡              (        x        )              =                            ∑                      i            =            31                    0                ⁢                              b            i                    ⁢                      x            i                              =                        l          ⁡                      (            x            )                          ⁢        mod        ⁢                  {                      g            ⁡                          (              x              )                                }                                l      ⁡              (        x        )              =                            ∑                      i            =            16511                    32                ⁢                              b            i                    ⁢                      x            i                    ⁢                      g            ⁡                          (              x              )                                          =                        x          32                +                  x          31                +                  x          4                +        1            
In the above-mentioned EDC operational formula, with reference to the ECD operation circuit shown in FIG. 15, EXOR circuits are disposed at the inputs of the 0th bit, 4th bit, and 31st bit of a 32-bit shift register. In the EXOR operation circuit, EXOR between a bit input from the most significant bit in the 4 bytes and the 31st bit, EXOR between the 3rd bit and the 31st bit, and EXOR between the 30th bit and the 31st bit are respectively calculated by the EXOR circuits.
As is understood from the above-mentioned EDC operational formula or the EDC operation circuit shown in FIG. 15, the EDC operation is a linear operation along the data recording direction (the C1 direction shown in FIG. 11).
When one sector having the structure as shown in FIG. 12 is inputted to the EDC operation circuit shown in FIG. 15, each for 4 bytes, in the data recording direction, i.e., in the order of ID area, IEC area, RSV area, user data area, and EDC area, the 32-bit shift register values obtained after the EDC area as the last 4 bytes is inputted becomes the EDC operation result.
As described above, conventionally, the method of performing error detection (EDC) after performing error correction (ECC) has commonly been employed. In this method, however, since error detection is carried out after an ECC block as one unit for error correction has been read from a buffer and subjected to error correction, the ECC block must be reread from the buffer, leading to problems such as consumption of the band width of the memory buffer, and increase in the processing time.
As a method for solving the problems such as consumption of the band width of the memory buffer and increase in the processing time, it is thought that the both processings of ECC and EDC are simultaneously carried out by reading an ECC block only one time from the buffer.
Since, as described above, the EDC operation is a linear operation along the data recording direction (C1 direction in FIG. 11), when error correction id carried out by the error correction circuit in the C1 direction in which the arrangement of the input data has continuity as shown in FIG. 13, it is possible to simultaneously perform the ECC in the C1 direction and the above-mentioned EDC. However, when error correction is carried out in the C2 direction in which the arrangement of the input data has no continuity as shown in FIG. 14, it is very difficult to simultaneously perform the ECC in the C2 direction and the EDC operation, and therefore, it is difficult to implement such simultaneous processings in a semiconductor.
The present invention is made to solve the above-described problems and has for its object to provide an error detection apparatus and an error detection method which can perform error correction and error detection simultaneously even when target code strings to be subjected to error detection in an ECC block are inputted in an arrangement having no continuity (C2 direction in FIG. 11).